1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of spacing the source drain extensions from the gate edge to lower the gate to source drain extensions capacitance in the fabrication of integrated circuits.
2. Description of the Prior Art
As the physical geometry of semiconductor devices shrinks, the channel length of the transistor is reduced as well. This leads to serious short channel effects. Lateral dopant diffusion from the source/drain extensions into the channel underlying the gate electrode will affect the threshold voltage and transistor current drive, thus affecting the device performance. Current practice involves spacing the source/drain extensions (SDE) from the gate edge using an offset spacer to lower the overlap capacitance between the gate and the SDE. However, it is desired to find a method to further lower the gate to SDE capacitance in situations where the offset spacer alone is insufficient.
U.S. Pat. No. 6,117,712 to Wu discloses a disposable spacer process for making raised source/drain devices. U.S. Pat. No. 6,127,234 to Gardner et al shows a shallow extension process using disposable spacers. U.S. Pat. No. 6,010,929 to Chapman teaches forming a nitride cap over the gate with extensions over the SDE region to space the source/drain regions from the gate.
A principal object of the present invention is to provide an effective and very manufacturable method of forming an integrated circuit device having low overlap capacitance transistors.
A further object of the invention is to provide a method of forming a transistor having low overlap capacitance by reducing effective dielectric constant value of the dielectric at the overlap between the gate and the source/drain extensions.
Yet another object is to provide a method of forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to reduce effective dielectric constant value of the dielectric at the overlap between the gate and the source/drain extensions.
In accordance with the objects of this invention a method for forming a transistor having low overlap capacitance by forming a microtrench at the gate edge to minimize lateral dopant diffusion is achieved. A gate electrode is provided overlying a gate dielectric layer on a semiconductor substrate wherein a hard mask layer overlies a top surface of the gate electrode layer. An oxide layer is formed overlying the semiconductor substrate. First spacers are formed on sidewalls of the gate electrode and overlying the oxide layer. Source/drain extensions are formed in the substrate using the first spacers as a mask. Second spacers are formed on the first spacers being comprised of a material different from the first spacers. Source/drain regions are formed in the substrate using the first and second spacers as a mask. A dielectric layer is deposited overlying the gate electrode and the oxide layer and planarized to the hard mask layer whereby the first and second spacers are exposed. The exposed second spacers are removed whereby the oxide layer underlying the second spacers is exposed. The exposed oxide layer is removed whereby the semiconductor substrate underlying the second spacers is exposed. The exposed semiconductor substrate is etched into to form a microtrench wherein the microtrench undercuts the gate oxide layer at an edge of the gate electrode. The microtrench is filled with an epitaxial oxide layer and planarized to the hard mask layer. The dielectric layer is patterned to form third spacers on the epitaxial oxide layer. The effective dielectric constant at the overlap between the gate and the source/drain extensions is reduced by the microtrench thereby completing formation of a transistor having low overlap capacitance in the fabrication of an integrated circuit device.